Various integrated circuits including one or more high-voltage transistors along with low-voltage circuits are in wide usage in diverse electrical applications. The high voltage transistors such as, for example, an extended drain MOS (EDMOS) transistor, a laterally double diffused MOS (LDMOS) transistor and the like occupy significant space in such integrated circuits.
In order to keep pace with the higher integration density trend, the high-voltage semiconductor devices also need to be scaled down in size while still maintaining sufficient operation characteristics.
Illustrated in FIG. 1A in plan view is a conventional extended drain MOS (EDMOS) transistor. FIG. 1B is a cross-sectional view along the line X-X′ of FIG. 1A, whereas FIG. 1C is another cross-sectional view along a line Y-Y′ of FIG. 1A.
Referring to FIGS. 1A to 1C, the conventional EDMOS transistor includes active regions 22, a P-type impurity region 14, a gate electrode 20, a gate insulation layer 19, an N-type drain region 16, an N-type source region 17, and a P-type pick-up region 18. An active region 22 includes an N-type second well 12 formed over a substrate 11 and a P-type first well 13 formed in the N-type second well 12. The P-type impurity region 14 junction-isolates adjacent active regions 22. The gate electrode 20 crosses the P-type first well 13 and the N-type second well 12. The gate insulation layer 19 is interposed between the gate electrode 20 and the substrate 11. The N-type source region 17 is formed in the P-type first well 13 adjacent one end of the gate electrode 20. The N-type drain region 16 is formed in the N-type second well 12, and is spaced apart from the gate electrode 20. The P-type pick-up region 18 is formed in the P-type first well 13, and is spaced apart from the N-type source region 17.
As adjacent active regions 22 are junction-isolated from one another by the P-type impurity region 14 of the conductive type different from the N-type second well 12, such a conventional EDMOS transistor has the drawback of requiring a non-operation region in addition to the P-type impurity region 14 in order to ensure the isolation between the active regions 22 that may have different electrical potential from one another, and to also allow a sufficiently high operating voltage of the active regions 22.
That is, although the non-operation region is not involved in the actual operation of the EDMOS transistor, such non-operation region is nevertheless needed to allow the adjacent active regions 22 to operate at sufficient voltage and in isolation form one another. The non-operation region dictates the EDMOS transistor pitch, which may be defined as an area obtained by subtracting the operation region from the entire device region, where the operation region is the area defined by the multiplication of the operation length L1 by the operation width W1, and is the region in which actual carrier transfer occurs in the EDMOS transistor between operation, and where the entire device region is the area defined as the multiplication of the device length L2 by the device width W2.
The need for the inclusion of the non-operation region makes it difficult to increase the integration density of the EDMOS transistor. This may not be a problem associated with only the EDMOS transistor, but may be a common problem for all junction-isolated high-voltage semiconductor devices.